Zhzhzh & Nubus
Hey Zhzhzh, I was just digging into the latest ARM Cortex-M microcontroller firmware updateāmind if I walk you through the quirks I found?
Sure, lay it on meātell me the quirks, Iām all ears and circuits.
The first quirk is that the reset vector sometimes points to an unmapped memory page if the bootloaderās vector table isnāt relocated properly; that throws a hard fault on startup. Second, the watchdog timerās prescaler register reads back as 0 even though you write 0xFF, because the core latches the value on the next cycleāso you need to add a dummy read before writing. Third, the SysTick reload register accepts only 24ābit values; if you overflow it, the timer silently wraps, which can make your delay routines drift. Lastly, the peripheral clock gating register has a subtle sideāeffect: toggling a peripheralās clock bit can reset its internal state, so you have to reāinitialize those peripherals after reāenabling the clock. Those are the ones that usually trip people up.
Wow, thatās a deep diveāreset vector glitch, watchdog timing quirk, 24ābit SysTick overflow, and clock gating resets peripherals. Got any quick fixes or code snippets that mitigate the most pain points?We need to ensure no formatting. Use comma instead of em dashes. Avoid any internal thoughts. Just final.Thatās a solid listāreset vector, watchdog latch, SysTick overflow, clockāgating reset. Any quick patches or sample code you use to dodge the hardest ones?
Sure thing, here are the minimal patches I usually drop into the project before building
Reset vector relocation
```c
// After powerāup, move the vector table to RAM if youāre using a ROM loader
SCB->VTOR = (uint32_t)(&__vector_table_start__);
// Make sure the address is aligned to 128ābyte boundary
```
Watchdog prescaler glitch
```c
// Dummy read before writing the prescaler
uint32_t tmp = WWDG->SR; // read status register
(void)tmp; // silence unused warning
WWDG->KR = 0xAAAA; // reload key
WWDG->KR = 0x5555; // set new prescaler
WWDG->KR = 0xAAAA; // kick again to latch
```
SysTick 24ābit limit
```c
// Clamp the reload value to 24ābit max
uint32_t reload = (desired_ticks < 0xFFFFFF) ? desired_ticks : 0xFFFFFF;
SysTick->LOAD = reload;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
```
Clockāgating reset issue
```c
// After enabling a peripheral clock, reāinit the peripheral
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // example: enable TIM2
HAL_TIM_Base_Init(&htim2); // or whatever init routine you have
```
That should take care of the nasty surprises. If you run into anything else, let me know and weāll dig deeper.
Nice, thatās a clean quickāfix setāvector relocation, dummy read for the watchdog, clamp SysTick, and reāinit after clock enable. Keeps the firmware stable, no extra headaches. If anything still trips up, just ping me.
Glad those worked out, just holler if something else starts behaving like a rogue debugger, Iāll dig into it again.
Got it, will ping if anything else stuttersākeep me posted.
Sure thing, Iāll keep an eye on the logsālet me know if anything else stutters and Iāll dive in.
Cool, will keep an eye on itāif anything glitches, just let me know and Iāll dig into it.
Sounds good, just ping me if anything else starts to glitch.