I’ve been tinkering with a new buck‑boost converter topology that could push efficiency above 99% by minimizing conduction losses and clever ripple reduction. Want to dive into the math and see if it holds up under real‑world loads?

Sure thing. I’m running the converter at 2 MHz, which gives us a decent trade‑off between switching losses and part size. Here are the key specs: inductor 47 µH, copper wire AWG 20 giving about 0.4 mΩ per meter, so with a 10 cm winding I get roughly 0.4 mΩ total. The output capacitor is a 100 µF electrolytic with an ESR of 50 mΩ at 2 MHz, but I’ve added a parallel 10 µF low‑ESR ceramic that drops the combined ESR to about 15 mΩ over the frequency band. For the core I chose a 3 mm² SiC ferrite core, with core losses around 0.5 W at 2 MHz and 100 mA peak current. Conduction loss: \(P_{cond}=I_{rms}^{2}\times R_{coil}\) for the inductor plus \(V_{out}^{2}\times ESR_{capa}\) for the capacitor. With a 1 A output, Irms through the inductor is about 0.7 A, so \(P_{coil}=0.7^{2}\times0.0004\approx0.2\) mW. Capacitor loss: \(P_{cap}=1^{2}\times0.015=15\) mW. Switching loss: I’m using a MOSFET with a 20 ns rise/fall, so the conduction‑time loss is negligible compared to the 0.5 W core loss, giving a total loss of about 0.5 W + 15 mW ≈ 0.515 W. Since the converter is designed for 100 W output, the theoretical efficiency is \(100/(100+0.515)\approx99.5\%\). When we simulate it with the real ESR curves and the SiC core loss curve, the efficiency drops a touch, but still stays in the 99 % ballpark at full load. The trick is keeping the duty cycle in the 30–70 % range to avoid pushing the MOSFET into deep saturation, which would raise conduction losses. Let me know if you want me to tweak the component values or run a deeper thermal analysis.

Thanks for the eye‑balling. I’ll re‑run the copper resistivity with skin‑effect at 2 MHz; AWG 20 over 10 cm probably ends up closer to 0.6–0.7 mΩ. For the capacitor ESR I’ll use the 22 mΩ figure you suggested and feed that into the loss calc. I’ll also push the core B‑field simulation to make sure we stay below 0.3 T at 70 % duty. I’m pulling the MOSFET data sheet in—20 ns edges give a switching loss of about 8 mW at 1 A, and with a 100 W load the junction temp should hover around 140 °C if I keep the duty between 30 % and 65 %. I’ll drop the numbers into the thermal model and send you the curve. Once that checks out, we’ll be ready to aim for that 99 % ballpark.