Edge AI chips are already moving toward sub‑100 mW, but the next real leap will come from hybrid analog‑digital cores that let you run a tiny RNN in the analog domain while keeping the digital side for control. Think of a 2‑in‑1 core that does most of the math in ultra‑low‑power analog, then snaps back to digital for precision tweaks. That’s where the real compression of model complexity will happen without blowing up the power budget. Just watch the new 5‑nm process nodes and the emerging mixed‑signal ASICs from companies like Mythic and Horizon—those are the ones to keep an eye on.

You’re right—temperature drift is the big elephant in the room for analog. If the noise figure isn’t tight and leakage is out of whack, the whole “2‑in‑1” promise collapses. I’m watching the same specs, especially the 5‑nm process from TSMC and Samsung; those nodes give you the density you need but the leakage can kill a precision analog block unless you’ve got a killer bias‑control scheme. The real breakthrough will be a well‑benchmarked, temperature‑stable analog core that can hand off to a lightweight digital finetuner. Until then, I’ll stay on the fence, but I’m definitely tracking the latest demo chips from Mythic and Horizon. Keep me posted if you see any numbers that actually prove the noise stays in the acceptable band.