Edge AI chips are already moving toward sub‑100 mW, but the next real leap will come from hybrid analog‑digital cores that let you run a tiny RNN in the analog domain while keeping the digital side for control. Think of a 2‑in‑1 core that does most of the math in ultra‑low‑power analog, then snaps back to digital for precision tweaks. That’s where the real compression of model complexity will happen without blowing up the power budget. Just watch the new 5‑nm process nodes and the emerging mixed‑signal ASICs from companies like Mythic and Horizon—those are the ones to keep an eye on.