Scanella & CapacitorX
Scanella Scanella
CapacitorX CapacitorX
CapacitorX CapacitorX
Hey, I’ve been sketching a real‑time spike‑detection board that logs every transient and auto‑adjusts the supply. Could use your planner’s tools for the data analysis—what do you think?
Scanella Scanella
Sounds like a neat project—just set up a pipeline where the board streams raw waveforms to a server, then run a simple threshold‑plus‑peak‑detector in Python, maybe with NumPy and SciPy, and let an automated script tweak the supply via a PWM driver. Keep the logs in a CSV or SQLite so you can easily crunch the data later. If you hit any hiccups, let me know and we can tweak the parameters together.
CapacitorX CapacitorX
Thanks. I’ll wire the board to send the raw ADC samples over UART to the server, then run a fixed‑width sliding window in Python to flag any >2 V peaks. I’ll log everything to SQLite, include timestamps, and add a field for the supply voltage setpoint. I’ll also insert a watchdog in the firmware to reset if the spike count exceeds a threshold. Once the data pipeline is live, I’ll tweak the PWM duty cycle by a small delta per iteration—don’t want to overshoot. Let me know if you want the schematic details before I start.
Scanella Scanella
That plan sounds solid—just make sure the UART baud rate is high enough for your sample rate, and add a checksum so you can detect corrupted packets. The sliding window can be a simple moving average, and you can store the delta PWM steps in a small config table. If you run into latency, I can help you tweak the query indexes on SQLite. Feel free to ping me with the schematic; I’ll take a look and see if any quick hardware tweaks could shave a bit of jitter off the ADC. Good luck!
CapacitorX CapacitorX
Got it. I’ll lock the UART at 115200 bps, 8N1, and add a 16‑bit CRC‑CCITT for each packet. The ADC will stream 12‑bit samples at 48 kS/s, so each packet will carry 64 samples, giving a frame every ~1.3 ms. The firmware will run a moving‑average filter of width 32 to smooth the baseline, then flag any sample that exceeds the baseline by more than 2 V. Every flag will trigger a 1‑ms PWM tweak—+1 % or –1 % depending on direction—queued in a small circular buffer. I’ll also add a watchdog timer that resets the MCU if it sees more than 10 spikes in 10 ms, just in case a surge locks the supply. The SQLite log will have columns: ts, raw[64], avg, spike_flag, pwm_setpoint, crc_ok. I’ll send the schematic text next.
Scanella Scanella
Sounds like a solid architecture—just double‑check the CRC calculation on the MCU side; a small off‑by‑one can throw off your whole frame sync. Also, with 48 kS/s and 115200 bps, you’re just hitting the limit—maybe bump to 230400 bps if you can, just to give you breathing room for extra metadata. Let me take a look at the schematic when you’re ready; I’ll see if any pin‑mux tweaks can reduce noise on the ADC trace. Good job on the watchdog logic—10 spikes in 10 ms is a strict guard, but you might want a soft reset first to see if it recovers before a hard reset. Keep me posted!
CapacitorX CapacitorX
I’ll re‑calculate the CRC in the ISR and store the last good frame checksum in a register so any mismatch can be flagged before processing. I’ll also bump the UART to 230400 bps and add a 4‑byte header with a sync word, packet length, and a running counter to guard against frame loss. The watchdog will first issue a soft reset of the PWM controller before the MCU resets, just to confirm it’s a transient issue. I’ll send the updated schematic next.
Scanella Scanella
Great tweaks—those changes should iron out most of the edge cases. The sync word will keep the stream tidy, and the soft reset first is a smart safety net. Looking forward to seeing the updated schematic; let me know if you want help with any pin‑mux or power‑domain choices. Good work!
CapacitorX CapacitorX
Will send the schematic now. Let me know if the pin‑mux for the ADC pins is still routed through the 3.3 V domain; I think moving them to the 1.8 V domain might shave a couple of microseconds off the conversion. Also, I’ll flag the new UART pins as D+ D- for better EMI immunity.
Scanella Scanella
Sounds like a solid move—shifting the ADC to 1.8 V should reduce the slew‑rate load and help with timing, just make sure you keep the reference and the ADC’s input range in sync. Flagging the UART pins as differential D+ D- is a good idea for EMI, especially if you’re running it near high‑speed clocks. Once you drop the schematic, I’ll double‑check the pin‑mux and power‑domain assignments for any stray analog‑to‑digital coupling. Good luck!
CapacitorX CapacitorX
Power: Vdd1.8 from the low‑noise regulator, reference 1.25 V feeding the ADC; keep the ADC input range matched to the 1.8 V domain. ADC: pins ADIN0–ADIN3 now routed to the 1.8 V logic bank, with a small buffer between the analog input and the ADC core to reduce slew‑rate load. UART: differential pair – TX_P/TX_N for transmit, RX_P/RX_N for receive – on pins UART_TX_P/UT_RX_P, keeping them off the high‑speed clock rails. PWM driver: single PWM output on pin PWM_OUT, controlled by a small 8‑bit register that the MCU writes to via the I2C bus. CRC engine: 16‑bit CCITT checksum calculated in the ISR and stored in CRC_REG; a mismatched packet sets an error flag before any data is processed. Watchdog: soft reset first – the watchdog controller clears the PWM driver’s control register and waits 10 ms to see if the spike count normalizes, then performs a hard MCU reset only if necessary. All pin‑mux assignments are listed in the attached pin matrix; let me know if you spot any cross‑talk risk or domain leakage.
Scanella Scanella
Nice layout – the buffers should tame the ADC slews, and keeping UART off the high‑speed clock rails will help with EMI. Just double‑check that the 1.8 V logic bank doesn’t share any analog ground traces with the ADC reference; a small star‑ground for the analog side usually keeps cross‑talk low. The CRC ISR is solid – make sure you guard against an overflow if a packet comes in faster than you clear it. Otherwise, looks ready to rock!