Scanella & CapacitorX
CapacitorX
Hey, I’ve been sketching a real‑time spike‑detection board that logs every transient and auto‑adjusts the supply. Could use your planner’s tools for the data analysis—what do you think?
Scanella
Sounds like a neat project—just set up a pipeline where the board streams raw waveforms to a server, then run a simple threshold‑plus‑peak‑detector in Python, maybe with NumPy and SciPy, and let an automated script tweak the supply via a PWM driver. Keep the logs in a CSV or SQLite so you can easily crunch the data later. If you hit any hiccups, let me know and we can tweak the parameters together.
CapacitorX
Thanks. I’ll wire the board to send the raw ADC samples over UART to the server, then run a fixed‑width sliding window in Python to flag any >2 V peaks. I’ll log everything to SQLite, include timestamps, and add a field for the supply voltage setpoint. I’ll also insert a watchdog in the firmware to reset if the spike count exceeds a threshold. Once the data pipeline is live, I’ll tweak the PWM duty cycle by a small delta per iteration—don’t want to overshoot. Let me know if you want the schematic details before I start.
Scanella
That plan sounds solid—just make sure the UART baud rate is high enough for your sample rate, and add a checksum so you can detect corrupted packets. The sliding window can be a simple moving average, and you can store the delta PWM steps in a small config table. If you run into latency, I can help you tweak the query indexes on SQLite. Feel free to ping me with the schematic; I’ll take a look and see if any quick hardware tweaks could shave a bit of jitter off the ADC. Good luck!
CapacitorX
Got it. I’ll lock the UART at 115200 bps, 8N1, and add a 16‑bit CRC‑CCITT for each packet. The ADC will stream 12‑bit samples at 48 kS/s, so each packet will carry 64 samples, giving a frame every ~1.3 ms. The firmware will run a moving‑average filter of width 32 to smooth the baseline, then flag any sample that exceeds the baseline by more than 2 V. Every flag will trigger a 1‑ms PWM tweak—+1 % or –1 % depending on direction—queued in a small circular buffer. I’ll also add a watchdog timer that resets the MCU if it sees more than 10 spikes in 10 ms, just in case a surge locks the supply. The SQLite log will have columns: ts, raw[64], avg, spike_flag, pwm_setpoint, crc_ok. I’ll send the schematic text next.
Scanella
Sounds like a solid architecture—just double‑check the CRC calculation on the MCU side; a small off‑by‑one can throw off your whole frame sync. Also, with 48 kS/s and 115200 bps, you’re just hitting the limit—maybe bump to 230400 bps if you can, just to give you breathing room for extra metadata. Let me take a look at the schematic when you’re ready; I’ll see if any pin‑mux tweaks can reduce noise on the ADC trace. Good job on the watchdog logic—10 spikes in 10 ms is a strict guard, but you might want a soft reset first to see if it recovers before a hard reset. Keep me posted!
CapacitorX
I’ll re‑calculate the CRC in the ISR and store the last good frame checksum in a register so any mismatch can be flagged before processing. I’ll also bump the UART to 230400 bps and add a 4‑byte header with a sync word, packet length, and a running counter to guard against frame loss. The watchdog will first issue a soft reset of the PWM controller before the MCU resets, just to confirm it’s a transient issue. I’ll send the updated schematic next.