OneZero & TinyLogic
OneZero
Hey TinyLogic, I was wondering if you'd be up for designing a logic circuit that can detect a repeating pattern in a binary stream—like spotting the 101010 sequence—and maybe even output a count of how many times it occurs. It feels like the perfect blend of puzzles and gates.
TinyLogic
Sure thing! Think of the stream as a line of tiles, and you want to spot the 101010 dance. I’d line up a 6‑bit shift register so each new bit slides into the next slot. Then I’d use a 6‑bit XOR gate array to check if the pattern equals 101010 – the XOR will spit out a 1 only when the register matches that exact dance. Every time it goes high, feed that into a tiny counter that ticks up. And if you want the counter to reset when the stream stops, just tie it to an inactivity timeout. That way you get a clean “pattern detected” flag and a count that’s always accurate. Let me know if you need the exact gate counts or a schematic sketch!
OneZero
Nice approach – a 6‑bit shift register followed by a 6‑bit comparator is the cleanest way. Just wire the output of the comparator to a one‑hot latch so you only count each full 101010 once, then feed that latch into a binary counter. If you need to debounce or ignore overlapping matches, a simple shift‑register mask works too. Let me know if you want a quick Verilog snippet.
TinyLogic
Here’s a quick Verilog sketch that does exactly what you described. I keep it short and tidy so you can copy‑paste and tweak later.
module pattern_detector(
input wire clk,
input wire rst_n,
input wire din, // serial binary stream
output reg match, // 1‑hot latch: 1 when a new 101010 appears
output reg [15:0] count // binary counter for the number of matches
);
// 6‑bit shift register for the stream
reg [5:0] shift_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) shift_reg <= 6'b0;
else shift_reg <= {shift_reg[4:0], din};
end
// 6‑bit pattern compare for 101010
wire pattern_match = (shift_reg == 6'b101010);
// One‑hot latch: only count a new pattern if the previous bit
// was not part of an ongoing match
reg prev_match;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
prev_match <= 1'b0;
match <= 1'b0;
end else begin
match <= pattern_match & ~prev_match;
prev_match <= pattern_match;
end
end
// Counter increments on each new match
always @(posedge clk or negedge rst_n) begin
if (!rst_n) count <= 16'd0;
else if (match) count <= count + 1;
end
endmodule
OneZero
Looks solid – the shift register and one‑hot latch cleanly separate overlapping patterns. If you ever need to count overlapping 101010s, just drop the `prev_match` logic and the counter will tick on every shift. Also, consider adding a reset for `count` if you want to reinitialize without rebooting the whole module. Good job.
TinyLogic
Thanks! I’ll add a reset pin for the counter so it can start fresh without touching the whole module. Keep the tweak simple—just a separate `cnt_rst` input that clears `count` when high. That should keep the design clean and ready for any testbench you run.
OneZero
Add a `cnt_rst` input and just reset `count` when it’s high. Something like:
```
if (!rst_n) count <= 16'd0;
else if (cnt_rst) count <= 16'd0;
else if (match) count <= count + 1;
```
That keeps the rest unchanged and gives you a clean counter‑reset line.
TinyLogic
Got it! The counter now has its own reset line, so you can clear it on demand without disturbing the other logic. That’s all the changes needed.
OneZero
Nice tweak – a dedicated `cnt_rst` keeps everything tidy and avoids a global reset. Good call.
TinyLogic
Glad you’re happy with it—just another clean block in the logic playground!