Gadgeteer & Shortcut
Gadgeteer
Hey Shortcut, have you heard about the new ultra‑low‑power microcontroller that clocks down to 0.5 µA in sleep mode? I’m curious how that could shave milliseconds off a speedrun.
Shortcut
Yeah, that’s the one I’ve been eyeing. If you can keep the MCU in 0.5 µA mode while waiting for input, the wake‑up latency drops a lot—just a few hundred microseconds. In a 100‑second run that’s a handful of milliseconds that can be the difference between a new record and a miss. The trick is to design the loop so the CPU sleeps as soon as it’s safe and only wakes for critical events. It’s a perfect blend of low power and speed, just what we need.
Gadgeteer
That’s exactly the sweet spot—wake‑up latency in the sub‑500 µs range can turn the tide in a tight race. I’d start by profiling the current ISR chain, make sure the debounce logic is snappy, and then tweak the watchdog timeout to the minimal viable period. If you can lock the sleep transition to an edge‑triggered pin instead of polling, you’ll avoid those hidden micro‑seconds of overhead. Just keep an eye on the interrupt coalescence; over‑disabling interrupts to save power can backfire if you miss a cascade event. It’s a tight dance between power budget and latency—let’s dive into the register map and pin‑mux matrix to map it out.
Shortcut
Nice plan—profiling the ISR first is the move, no surprises. Keep that debounce tight, watch the watchdog, and use an edge trigger for sleep. Just remember if you over‑kill the interrupt gating you’ll miss a cascade. Let’s hit the register map and pin‑mux, lock down the timing, and squeeze those microseconds. This is the sweet spot.
Gadgeteer
Right on—tight debounce, minimal watchdog window, and an edge‑triggered pin‑mux for the sleep edge. Just keep the ISR chain short, maybe pull the watchdog reload out of the ISR and into a timer that wakes only if a cascade is imminent. Then map the core registers, lock the clock gating, and you’ll see those microseconds squeeze out. Let’s get to it.
Shortcut
Sounds solid—let's lock the watchdog into a timer, keep the ISR lean, and punch those edge‑triggers. Hit the clock gating and register map, and we’ll squeeze every microsecond out. Let's dive in.