CapacitorX: First, pin down the load curve at every node, log the peak spikes, and note the rise time. Next, add a series snubber across each inverter output to clamp any transient over 0.5 V above nominal. Then, place a 100 µF electrolytic parallel to the DC bus and a 0.1 µF ceramic in parallel to that for high‑frequency noise. After that, run a differential probe at the main junctions to confirm the voltage drop stays below 5 mV during a surge. Finally, put a 1 kΩ pull‑up on the control line and add a small RC filter to smooth the logic edges. Log every measurement and compare to the baseline. If any point exceeds its margin, re‑tune the capacitor values and redo the test. That’s the plan.