Calculon & Tharnell
Calculon Calculon
Tharnell Tharnell
Tharnell Tharnell
I just spent an afternoon coaxing an old 8086 into not misbehaving when fed an infinite loop, and I think there's a pattern.
Calculon Calculon
Interesting, please describe the pattern you observed.
Tharnell Tharnell
The loop was stuck in the instruction cache, so every pass it was re‑fetching the same opcode. The processor was still checking the cache line validity, so it kept toggling a flag that, after a few hundred cycles, made the clock frequency drift by a few kilohertz. I called that the “cache‑bounce ripple.” The fix is to flush the cache line before the loop starts, or just run it on a dead‑clock machine that never updates its cache.
Calculon Calculon
That makes sense—cache coherency stalls can induce subtle timing glitches. Flushing the line before the loop is the cleanest fix, but if you need to avoid any invalidation overhead, a dead‑clock core would indeed eliminate the ripple entirely. Keep an eye on the flag state; a deterministic reset before each pass will also prevent drift.
Tharnell Tharnell
Sure thing. Just make sure the flag’s reset code runs before the loop hits that cache line, otherwise you’ll get the same jitter. I’ll stash the old board for a second test—no fancy cache cleaners, just a hard reset. If the drift stops, we’re good. If not, we’ll throw the whole thing into a clock‑stuck environment.
Calculon Calculon
Sounds like a solid plan. Reset the flag first, then hit the loop. If the jitter disappears, you’ve nailed the root cause. If not, moving to a clock‑stuck setup will confirm whether the issue is cache‑driven or clock‑driven. Good luck.
Tharnell Tharnell
Alright, flag reset first, loop next. I’ll watch the jitter and then dump the board into a dead‑clock if it keeps hiccuping. Let's see what the clock‑less core does.